RISC-V ARCHITECTURE TRAINING

RISC-V ARCHITECTURE

RISC-V ARCHITECTURE

Reference : R5_ARCH
Course families : Processors > RISC-V Processors > RISC-V ARCHITECTURE
Target Audience : Architects, verification engineers, software developers
Duration : 5 days, 7 hours a day

For more information and a detailed agenda about this course, please contact us

Contact us

Training location & format

For dedicated sessions at your training facilities, content can be tailored to further meet your needs
(Contact us for public workshops)
Certificate of Completion

A Certificate of Completion will be delivered upon completion of the training course
Related products

Risc-V software package, contact us for detailed description

Learning Objectives

This course explains the Risc-V 32- and 64-bit architecture and does not target a particular Risc-V core. It enables participants to efficiently design core and subsystem compliant with a particular Risc-V profile, verify it, and develop low level software, implementing the features offered by the architecture: exceptions, low power modes, assembly language. Latest specifications, such as smMTT and AIA are covered
Prerequisites and related courses

Basic knowledge of a CPU or DSP.
Refer to our course on PCIe CVT_GP_PCIE6 for PASID, ATS and PRI specifications.
Refer also to ARM_AMBA_AXI for understanding atomic and exclusive operations.
Hands-on

Based on Microchip ICICLE board. GCC toolchain, Trace32 debugger.

Program Overview

DAY 1

PRIVILEGE MODES AND MEMORY PROTECTION
PHYSICAL MEMORY PROTECTION (PMP) AND PHYSICAL MEMORY ATTRIBUTES (PMA)
WORLDGUARD SECURE PLATFORM ARCHITECTURE
SUPERVISOR DOMAIN ACCESS PROTECTION (SmMTT)
RISC-V ARCHITECTURE

DAY 2

USER PROGRAMMING
FLOATING-POINT UNIT
VECTOR EXTENSION
SUPERVISOR PROGRAMMING
HYPERVISOR PROGRAMMING
OPENSBI

DAY 3

GCC TOOLCHAIN RISC-V SPECIFIC FEATURES
EXCEPTION MECHANISM
CORE LOCAL INTERRUPTOR (CLINT)
PLATFORM-LEVEL INTERRUPT CONTROLLER- (PLIC)
EXTERNAL BUS PORTS- TILELINK PROTOCOL
CACHE SOFTWARE MANAGEMENT

DAY 4

MEMORY MANAGEMENT UNIT
IOMMU
ADVANCED INTERRUPT ARCHITECTURE- (AIA)
BOOTING A CORE

DAY 5

DATA AND INSTRUCTION PATHS, EXCLUSIVE RESOURCE MANAGEMENT
POWER MANAGEMENT
INVASIVE DEBUG FEATURES
NON-INVASIVE DEBUG FEATURES

MOVE.B IS MORE THAN A TRAINING CENTER

Trainers are also experts able to assist customers throughout the design process.
They also provide consulting services, design support and assistance.
Therefore, our trainers contribute to the success of our customers’ industrial projects by leveraging all of the technologies they master and teach.

Consulting & Solutions

Learning Delivery Methods

Alternating lectures, trainer-driven hands-on practical examples, group interactions with the trainer, and self-reflection time.

Learning Evaluation

Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course

Trainers’ Profile and Expertise

Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases

Course Documentation

Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content