Reference : R5_32B_E31
Course families : Processors > RISC-V Processors
Target Audience : Architects, Verification engineers, Software developers
Duration : 2 days, 7 hours a day
CORE ARCHITECTURE
HARDWARE IMPLEMENTATION
INSTANTIATING THE CORE
PRIVILEGE LEVELS
DATA AND INSTRUCTION PATHS
INSTRUCTION CACHE AND TIGHTLY INTEGRATED MEMORIES
EXCEPTION MECHANISM
CORE LOCAL INTERRUPTOR (CLINT)
PLATFORM-LEVEL INTERRUPT CONTROLLER (PLIC)
USER PROGRAMMING
COMPILER OPTIONS
DEBUG FEATURES
Alternating lectures, trainer-driven hands-on practical examples, group interactions with the trainer, and self-reflection time.
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
RISC-V ARCHITECTURE RISC-V 64-BIT E51