Reference : CVT_GP_PCIE7
Course families : Connectivity > General purpose buses
Target Audience : Architects, board designers, verification engineers, characterization engineers, firmware developers
Duration : 6 days, 7 hours a day
INTRODUCTION TO PCI EXPRESS
SUMMARY OF PCIE GEN1-5 PHYSICAL LAYER
64 and 128 GTps PHYSICAL LAYER- LOGICAL SUB-BLOCK
64 and 128 GTps PHYSICAL LAYER- ELECTRICAL SUB-BLOCK
RETIMER
CHARACTERIZING A PCI EXPRESS INTERFACE
ASIC DESIGN- PIPE INTERFACE
MECHANICAL FORMATS
POWER MANAGEMENT
LINK LAYER STATE MACHINE
PACKET ROUTING
TLP ACKNOWLEDGEMENT
FLOW CONTROL
TRANSACTION ORDERING
UIO
QUALITY OF SERVICE
PACKET FORMAT
INTERRUPT MANAGEMENT
ERROR MANAGEMENT
THE CONFIGURATION SPACE
SYSTEM FIRMWARE INTERMEDIARY
SR-IOV AND FEATURES THAT FACILITATE I/O VIRTUALIZATION
SCALABLE I/O VIRTUALIZATION (SIOV)
ADDRESS TRANSLATION SERVICES (ATS)
PROTOCOL MULTIPLEXING
HOT PLUG
PRECISION TIME MEASUREMENT
ATOMIC TRANSACTIONS
SECURITY, INTEGRITY AND DATA ENCRYPTION
TEE DEVICE INTERFACE SECURITY PROTOCOL (TDISP)
Lectures with supporting slides, use of projector.
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
PCI EXPRESS GEN5 MOBILE PCI EXPRESS MPCIE