Reference : DRAM_LPDDR5
Course families : DRAM memories > LPDDR memories
Target Audience : Architects, board designers, verification engineers, validation engineers
Duration : 3 days, 7 hours a day
INTRODUCTION TO DRAM
LPDDR5 NEW FEATURES
LPDDR5 PACKAGE PINOUT & ADDRESSING
FUNCTIONAL DESCRIPTION
TRAINING PROCEDURES
- ZQ calibration, background or command-based
- CA VREF training
- DQ VREF training
- WCK2CK leveling, WCK2CK sync operation
- Duty Cycle Adjuster (DCA) and Duty Cycle Monitor (DCM)
- Command bus training
- RD DQ calibration
- WCK-DQ training
- WCK-RDQS_t/parity training
WCK2CK INTERVAL OSCILLATOR
LPDDR5 COMMAND DEFINITIONS AND TIMING DIAGRAMS
ON DIE TERMINATION (ODT)
ELECTRICAL CHARACTERISTICS
LPDDR5X EQUALIZATION
LOW POWER MODES
Lectures with supporting slides, use of projector.
Practical uses cases complement the theoretical explanations.
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
LPDDR4