Reference : DRAM_LPDDR6
Course families : DRAM memories > LPDDR memories
Target Audience : Architects, board designers, verification engineers, validation engineers
Duration : 3 days, 7 hours a day
INTRODUCTION TO DRAM
LPDDR6 NEW FEATURES
LPDDR6 PACKAGE PINOUT & ADDRESSING
FUNCTIONAL DESCRIPTION
TRAINING PROCEDURES
ON DIE TERMINATION (ODT)
LPDDR6 COMMAND DEFINITIONS AND TIMING DIAGRAMS
METADATA
SAFETY AND SECURITY FEATURES
LOW POWER MODES
LPDDR6 EQUALIZATION
TESTING
ELECTRICAL CHARACTERISTICS
Lectures with supporting slides, and use of projector.
Practical uses cases complement the theoretical explanations.
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
LPDDR5 / LPDDR5X