For dedicated sessions at your training facilities, content can be tailored to further meet your needs
(Contact us for public workshops)
Certificate of Completion
A Certificate of Completion will be delivered upon completion of the training course
This course explains the hardware and software architecture of the Cortex-A510 to enable participants to efficiently design a SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, virtualization and multicore.
CORTEX-A510 CLUSTER BASED ON DYNAMIQ SHARED UNIT
POWER AND RESET CONTROL WITH DSU-110 POWER POLICY UNITS
RELIABILITY, AVAILABILITY, AND SERVICEABILITY (RAS) EXTENSION
INTRODUCTION TO ARM ARCHITECTURE V9-A
AARCH64 EXCEPTION MANAGEMENT
MEMORY PARTITIONING & MONITORING (MPAM)
INTRODUCTION TO MEMORY MANAGEMENT UNIT
CORTEX-A510 IMPLEMENTATION DEPENDENT MMU FEATURES
SYSTEM MMU, MMU-600
GICv3, GICv4 AND LOW POWER MODES
A64 INSTRUCTION SET SUMMARY
V8.2-A NEW INSTRUCTIONS
SVE2 SIMD INSTRUCTION SET
EMBEDDED SOFTWARE DEVELOPMENT
MOVE.B IS MORE THAN A TRAINING CENTER
Trainers are also experts able to assist customers throughout the design process.
They also provide consulting services, design support and assistance.
Therefore, our trainers contribute to the success of our customers’ industrial projects by leveraging all of the technologies they master and teach.